IEEE Symposia on VLSI Technology and Circuits 2012

The IEEE Symposia on VLSI Technology and Circuits, from June 12 to 15 in Honolulu, Hawaii will have several in depth tracks focusing on ReRam and memristor based research. The two tracks have the following tentative schedules: please bookmark and check the VLSI Conference Website¬†(below) for the latest updates and information. A sampling of the […]

Noise and Variation Tolerant Multilevel Memristor Memory (MLMM) Systems, MRAM macros for Memory-in-Logic

Memristor related papers and abstracts from the 20th Great Lakes symposium on VLSI (May 16 – 18, 2010): Design considerations for variation tolerant multilevel CMOS/Nano memristor memory (Harika Manem, Garrett S. Rose, Xiaoli He, Wei Wang) examines, in part, unfolded crossbar memory noise margins and power consumption: “This work analyzes the design constraints for nanoscale […]