Memristor MOS Content Addressable Memory (MCAM) [archiv.org]
A new paper from IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL.X, NO.X, 201X titled “Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines” details the results of recent simulation matrices run on MCAM memristor models using a behavioral modeling approach; results on low power consumption in memory and fabrications silicon area reductions are exciting, to say the least:
Our simulation results show that the MCAM approach provides a 45% reduction in silicon area when compared with the
SRAM equivalent cell.The Read operation of the MCAM ranges between 5 ns to 12 ns, for various implementations, and is comparable with current SRAM and DRAM approaches. However the Write operation is signiﬁcantly longer. Simulation results indicate a reduction of some 96% in average power dissipation with the MCAM cell. The maximum power reduction is over 74% for the memristor-based structure. The RMS value of current sunk from the supply rail for the MCAM is also approximately 47 µA, which correspond to over a 95% reduction when compared to SRAM-based circuitry. To the best of our knowledge this is the ﬁrst power consumption analysis of a memristor-based structure
that has been presented using a behavioral modeling approach.
As the technology is better understood and matures, further
improvements in performance can be expected. [arxiv.org abstract link]
The full PDF of the paper can be read [HERE]. The authors, all IEEE members or fellows, are Kamran Eshraghian, Kyoung Rok Cho, Omid Kavehei, Soon-Ku Kang, Derek Abbott, and Sung-Mo Steve Kang.