Toshiba announces date for promised 24nm NAND flash
Toshiba (TAEC) announced the release dates today for their 24nm smartNAND NAND flash memory chips. These are the 48 pin TSOP (12mm x 20mm x 1.2mm), 52 land LGA (14mm x 18mm x 1.0mm) there had been talk about since last year: standard NAND flash memory interface, 8K Byte page size, 4 read and 2 write type modes, MLC of 2 bits/cell, ~2.7-3.6vs. They promise an improvement of 1.9 x faster read, 1.5 x write speeds over 32nm flash (note: source is Toshiba press release! mm hmm.). The following smartNAND size and release schedule is below:
Toshiba 24nm NAND Flash Production Release Schedule:
| 4GB | 48 pin TSOP | May, 2011 | 2Q, 2011 | |
| 52 land LGA | August, 2011 | 3Q, 2011 | ||
| 8GB | 48 pin TSOP | April, 2011 | 2Q, 2011 | |
| 52 land LGA | July, 2011 | 3Q, 2011 | ||
| 16GB | 48 pin TSOP | September, 2011 | 4Q, 2011 | |
| 52 land LGA | May, 2011 | 2Q, 2011 | ||
| 32G | 52 land LGA | June, 2011 | 3Q, 2011 | |
| 64GB | 52 land LGA | August, 2011 | 3Q, 2011 |
24nm is a very nice milestone. Any kind of improvement in scale and production helps get closer to improving the efficacy of ultra low power distributed sensor hardware. And a step closer to getting some of this real “big data” coming in. Of course, some of the more extreme SPICE and mathematics modelers have proposed terabits of data for memristors in a 12 x 12 mm package (including many FPGA functions). But THAT release schedule is not to be spoken of for at least ten years.
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