Memristor-based Nonvolatile Synchronous Flip-flop Latch Circuits (Journal of Nanotechnology)

The Nanotechnology Journal Volume 21, Number 23 is out online today with the short paper by Stan Williams et al submitted this last March that details more specifics about HP Labs early attempts at a nonvolatile, memristor based flip-flop latch circuit:

We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources.[iop article]

Interestingly, the tests are based on the HP Pt–TiO2–Pt on Si mix, and give some indications about possible endurance and threshold matrices, as far as the rough test model was concerned. The program test cycle ran for 400 no-error cycles, with increasing errors up to 1500 cycles, at which the memristor failed. Its important to note that many of these experiments are, in fact, exploratory, and thus not to be taken as functional prototyping. Tighter integration of CMOS and memory systems is what is being attempted here. Full pdf of the article is available [here], (registration required) with further details and specifics about the test design and performance.